Estudo de técnicas de codificação visando a otimização de circuitos digitais : um estudo de caso.

Abstract

This work tackles the study of a data communication integrated circuit, more specifically an integrated circuit for Ethernet data communication. Throughout the work, the design flow and commonly used CAD tools were studied focusing on the hardware description language Verilog and in special the logic synthesis results. Furthermore, the research of techniques for area, power consumption and frequency was conduced looking into the literature and conducing experiments to validate the results. The combination of different techniques to a case study allowed the analysis of the results and a comparison of them in terms of improvements obtained by each one. The analysis was made taking into account the implementation cost in terms of time length and complexity, gate count reduction, power and frequency on top of other pros and cons of each technique. Giving that, the result is a detailed comparison which allows one to choose and apply the techniques in order to obtain the desired product. The techniques can be easily employed and combined with other techniques in lower abstraction levels such as routing, physical synthesis and even in the fabrication process to achieve requirements in terms of area, power and frequency.