A SystemC behavioral model for delay variation analysis in asynchronous designs.

Abstract

The evolution of the manufacturing processes in the semiconductor industry are pushing the limits of physics every new technology generation. This growth represents a larger number of transistors per square inch in every generation. Today the predominant design style is synchronous design with complementary metal-oxide-semiconductor being the manufacturing standard. But, within the present decade, some of fundamental limits of physics are going to be reached. Thus, the manufacturing companies are always searching novel ways to overcome the rapid incoming challenges in the manufacturing technologies, e.g. transistor leakage in submicron processes and minimum transistor length limit. Even though there are many talented engineers, physicists and chemists, those limits are becoming more challenging every new manufacturing generation. Thus, new design styles appear as possible solutions, such as asynchronous circuits. However, this design style is still not mature enough in the market. There are some practical aspects that makes this style not attractive for design houses. For instance, asynchronous circuits have a higher timing requirement for verification and testing since they may have many timing assumptions that must be understood by the designers and well covered by verification tools. Therefore, the present thesis is going to focus in asynchronous circuits verification through the design of an environment for random wire and gate delays. This work will present a simulation framework built on top of SystemC that models asynchronous designs, where components of the design are mapped to a thread and are assigned to a delay value for each round of simulation. The logic functions of the design are verified with a predefined testbench, then the results are compared against the expected behavior to ensure the model remains working though the environment changes its characteristics. To perform the verification, the testbench runs the model many times with different delays for gates and wires, considering some limits in the operating conditions. The case study chosen for this thesis is a pipeline controller based on fundamental mode assumptions where the testbench will apply new input values to the controller just after its internal state has stabilized. The controller output logic functions are decomposed in gate networks that are mapped to SystemC modules. For each module, the inner components, including wire connections, are mapped into SystemC threads. The controller is simulated and a testbench representing a pipeline test is executed generating stimulus for the design. In the end, the testbench reports system measures and whether the design has passed or failed due to variability of the operating conditions.